The subject invention is directed generally to circuit testing, and more particularly to test circuitry for burn-in testing without the use of burn-in ovens and which is self-regulating as to burn-in temperature.
As is well known, integrated circuits exhibit most failures during early life and at the end of their useful life. Thus, integrated circuits tend to be most reliable between early life and the end of useful life. Many, if not most, integrated circuit early life failures can be accelerated by increased temperature. Accordingly, integrated circuits utilized in high reliability and military systems are commonly subjected to burn-in testing wherein an integrated circuit is placed in a burn-in oven that produces an in-oven ambient temperature that is intended to achieve a desired chip junction temperature. For example, for Military Specifications, junction temperature is required to be at least 125 degrees Celsius for 160 hours. Temperatures higher than 125 degrees Celsius may be selected with correspondingly reduced burn-in time. Burn-in junction temperature can therefore be selected to be between 125 degrees Celsius the device maximum temperature, with the increased temperature being traded against burn-in time.
During burn-in testing, the integrated circuit under test is powered (i.e., power is applied to the supply pins of the integrated circuit), and sometimes is operated (i.e., the integrated circuit under test is operated in its intended modes of operation). The former type of testing (power only) is referred to as static burn-in testing, and the latter (power and operation) is referred to as dynamic burn-in testing.
An important consideration with conventional burn-in testing is the control of burn-in temperature of the integrated circuits being tested by control of the oven ambient temperature. Maintaining a specified chip junction temperature is extremely difficult due to lack of knowledge of the specific characteristics of the thermal environment (ambient-to-package heat transfer and case-to-junction heat transfer), and lack of knowledge of the precise chip power dissipation during the burn-in process. Thus, conventional burn-in testing can result in under-screening by temperatures that are too low, or in overstress of the integrated circuit by temperatures that are too high.
Further considerations with conventional burn-in testing include the cost of burn-in ovens and their attendant complexity, and the inability to test an entire system which includes integrated circuits having different burn-in temperature requirements.